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        USERS' GUIDE

        HD-000288-UG-1- HB-Bipolar-DS-eval-board

         

        HEY-HBDS-G-12D1-D USERS'GUIDE

        HEY1011 HALF BRIDGE BIPOLAR DRIVER SWITCH BOARD

         

        Content

        DescriptionQuick Start GuideGate pull up and pull down resistorsEnable and start sequenceMeasurement pointsBipolar Gate drivePropagation delayDouble Pulse TestDouble pulse test resultsSchematicPCB LayoutBill of materialsOrdering InformationDisclaimer

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        Description

        The Heyday Integrated Circuits Half Bridge Driver-Switch HEY-HBDS-G-12D1-D is a demonstration board containing two HEY1011-L12 GaN FET drivers and two GaN FETs configured in a half bridge configuration.

        The datasheet for the HEY1011-L12 used in this board can be found here.

        HEY-HBDS-G-12D1-D fig1

        Figure 1: HEY-HBDS-G-12D1-D Evaluation Board

         

        The HEY-HBDS-G-12D1-D can be used to perform double pulse tests, or to interface the half bridge to an existing LC power section, both as shown below.

         The isolated HEY1011-L12 driver does not require secondary side power or bootstrap components. Gate drive power is supplied to secondary side from the primary side supply voltage VDRV. The amplitude of the gate drive can be varied by varying VDRV between 7 V and 15 V.

         


         

         

        hazard

         

        DANGER

        DO NOT TOUCH THE BOARD WHEN IT IS ENERGIZED AND ALLOW ALL COMPONENTS TO DISCHARGE COMPLETELY PRIOR HANDLING THE BOARD.

         HIGH VOLTAGE CAN BE EXPOSED ON THE BOARD WHEN IT IS CONNECTED TO POWER SOURCE. EVEN BRIEF CONTACT DURING OPERATION MAY RESULT IN SEVERE INJURY OR DEATH.

        Please ensure that appropriate safety procedures are followed. This evaluation kit is designed for engineering evaluation in a controlled lab environment and should be handled by qualified personnel ONLY. Never leave the board operating unattended.

        warning

         

        WARNING

        Some components can be hot during and after operation. There is NO built-in electrical or thermal protection on this evaluation kit. The operating voltage, current, and component temperature should be monitored closely during operation to prevent device damage.

        ESD

         

        CAUTION

        This product contains parts that are susceptible to damage by electrostatic discharge (ESD). Always follow ESD prevention procedures when handling the product. 

         

        Quick Start Guide

         

        HEY-HBDS-G-12D1-D fig2

         

        Figure 2: HEY-HBDS-G-12D1-D Quick Start

        1. Apply VDRV = 12V

        2. Link pins EN_PU and EN (if not using external Enable control)
        3. Apply input gate signals, with adequate dead time, to the IN_L and IN_H inputs.

        4. Convenient test points are located on the test board as shown above. A suitable differential oscilloscope should be used to monitor the high side gate signal from VGH to VSW.

        Gate pull up and pull down resistors

        The HEY1011-L12 gate driver has independent output pins for the gate pull up and gate pull down allowing control of the turn-on and turn-off rise and fall times.

        The default values for these resistors are:

        • OUTPU: R1 and R5 = 10 Ohms

        • OUTPD: R3 and R7 = 1 Ohm

        These values can be modified to suit your own application.

         

        Enable and start sequence

        The HEY1011-L12 has an open drain enable pin (EN) to facilitate a system level wired-AND start up.

        When the enable pin is externally pulled low this forces the driver into a low power mode. The driver output is pulled low in this mode. In the event of an internal fault condition, such as UVLO, this pin is actively pulled low internally by the driver. During normal operation, the pin is released by the driver, and must be pulled high with an external pull-high resistor. This functionality can be used by the PWM controller as an indication that it can start sending IN pulses to the driver. It is typically wired AND with the controller enable pin as shown in Figure 3 below.

         The HEY-HBDS-G-12D1-C EVM board provides direct access to the EN pin on connector CONN1. Internally the board contains a 100k pull up resistor connected from VDRV to the EN_PU pin on connector CONN1 – see schematic in Figure 12. If external control of the enable function is not required, pins EN and EN_PU must be linked together on CONN1 to make use of the internal 100k pull up resistor to enable the driver. If the EN pin is left floating, the drivers will not respond to INL or INH input signals.

        HEY-HBDS-G-12D1-D-fig3

        Figure 3: HEY1011-L12 Wired-AND enable

        The start up sequence of the HEY1011-L12 is shown in Figure 4 below. Time TSTART is defined as the time after which VDRV reaches the UVLO rising level to the HEY1011-L12 releasing the EN internal pull down.

         IMPORTANT the IN signal must not be applied before the EN pin has been released.

         

        HEY-HBDS-G-12D1-D-fig4

        Figure 4: HEY1011-L12 Start up sequence.

         

        Measurement points

         

        The HEY-HBDS-G-12D1-D EVM contains convenient test points for monitoring the high and low side gate drives as well as the switch node as shown in Figure 5 below.

        When measuring VGS_H use a differential probe with suitable ratings for the applied bus voltage. The HEY-HBDS-G-12D1-D EVM uses a bipolar gate drive arrangement as shown in Figure 6 below. When measuring VGS, both gate drives are measured relative to the source of their associated GaN FET. Therefore, the off-state voltage will be negative.

         It is important to use a low inductance scope probe ground lead as shown to avoid pickup of spurious switching noise.

        HEY-HBDS-G-12D1-D-fig5

        Figure 5: Measurement points

        Bipolar Gate Drive

        Due to the high rate of change of voltages and currents in power switching circuits, unwanted inductor currents and capacitor voltage drops can be created.

        One such example is the false turn on of a FET due to a dv/dt event. In a half bridge circuit, after the low side FET has been turned off and a suitable dead-time elapsed, the high side FET is turned on. This produces a rapidly changing switch node voltage at the drain of the low side FET. This voltage will produce a capacitor current:

        formulae

        flowing in the gate-drain capacitance, CGD, and driver output. It will cause the voltage on the gate of the low side FET to rise. If this voltage spike peaks beyond the threshold voltage VTH, the FET will conduct. Considering that the high side FET is also conducting, this can result in a potentially destructive shoot-through event.

        The HEY-HBDS-G-12D1-D EVM uses a bipolar gate drive arrangement which is useful to mitigate against the effects of gate-drain capacitor currents. The secondary supply voltage VSEC is a function of the primary supply voltage VDRV. The zener diode, CR1, will regulate the positive turn on voltage of the GaN FET. During the turn-off of period, the gate voltage will be negative with a value of:

        VGS_OFF = VSEC – VZENER. VSEC is typically 9 V.

         This negative VGS_OFF voltage allows more margin before the threshold voltage can be reached.

         HEY-HBDS-G-12D1-D-fig6

        Figure 6: Bi-polar gate drive schematic

         

        Propagation Delay

         

        • VDRV = 12V
        • Input = 100kHz
        • RPU = 10R, RPD = 1R
        • Power train un-loaded. That is, VHV+ = 0V.

        Figure 7a: Low side driver output
        HEY-HBDS-G-12D1-D-fig7a

         

        CH3: Low side driver input, CH1: Low side ddriver (IC2) outpout wrt VHV

        Figure 7b:Typical Turn-on Propagation Delay
        HEY-HBDS-G-12D1-D-fig7b

         

        CH3: Low side driver input, CH1: Low side ddriver (IC2) outpout wrt VHV

        Figure 7c: Typical Turn-off Propagation Delay
        HEY-HBDS-G-12D1-D-fig7c

         

        CH3: Low side driver input, CH1: Low side ddriver (IC2) outpout wrt VHV

        Figure 7: Typical Driver output at 100kHz

        Double Pulse Test

        Theory

        The double pulse test is used to evaluate the switching characteristics of a power switch under hard switching but in a safe manner.

        For a low side switch the set up is as shown below:

        HEY-HBDS-G-12D1-D-fig8

        Figure 8: Double Pulse Test

         

        The low side switch is driven with two pulses as shown below. The high side switch can be held off or driven with the inverse of the low side gate switch (with adequate dead time).

        HEY-HBDS-G-12D1-D-fig9

        Figure 9: Double Pulse Test Waveforms

         

        An inductor is placed in parallel with the high side switch. The goal of this inductor is to establish the test level current in the low side switch at the end of the first on pulse (1). The magnitude of the test level current at the end of period 1 is given by:

        formulae2

        During period 2, the inductor current will naturally decay. The duration of period 2 should not be too long that inductor current deviates significantly from the desired test level.

        During period 3, the inductor current will again rise. Period 3 should not be so long that the inductor current rises to an excessive level.

        The falling edge of pulse 1 is used to examine the hard turn off characteristics of the switch. The rising edge of pulse 3 is used to examine the hard turn on characteristics of the switch. By only applying these two pulses, the switches are only on for a very short time and should not overheat.

         

        Double Pulse Test Results

         

         COMPONENTS

        Drivers:

        Heyday HEY1011-L12C

        Inductor:

        49uH 360m Air Core

        RPU:

        10Ω

        RPD:

        1Ω

         

        DPT Result 100V – 15A

         

        Figure 10a: DPT Overview
        HEY-HBDS-G-12D1-D-fig10a

         

        CH1(red) : Low side driver input, CH2 (Grn): Switch node (500MHz probe), CH4 (Blu) Inductor current (1A/V)

        Figure 10b: Hard switching turn off
        HEY-HBDS-G-12D1-D-fig10b

         

        CH1(red) : Low side driver input, CH2 (Grn): Switch node (500MHz probe), CH4 (Blu) Inductor current (1A/V)

        Figure 10c:Hard switching turn on Time base (12.5ns/div)
        HEY-HBDS-G-12D1-D-fig10c

         

        CH1(red) : Low side driver input, CH2 (Grn): Switch node (500MHz probe), CH4 (Blu) Inductor current (1A/V)

         

        DPT Result 400V – 62A

         

        Figure 11a: DPT Overview
        HEY-HBDS-G-12D1-D-fig11a

         

        CH1(red) : Low side driver input, CH2 (Grn): Switch node (500MHz probe), CH4 (Blu) Inductor current (1A/V)

        Figure 11b: Hard switching turn off
        HEY-HBDS-G-12D1-D-fig11b

         

        CH1(red) : Low side driver input, CH2 (Grn): Switch node (500MHz probe), CH4 (Blu) Inductor current (1A/V)

        Figure 11c:Hard switching turn on Time base (12.5ns/div)
        HEY-HBDS-G-12D1-D-fig11c

         

        CH1(red) : Low side driver input, CH2 (Grn): Switch node (500MHz probe), CH4 (Blu) Inductor current (1A/V)

        Schematic

         

        HEY-HBDS-G-12D1-C-fig12

        Figure 12: HEY-HBDS-G-12D1-DHEY-HBDS-G-12D1-D-fig13 Schematic

         

         

        PCB Layout

        HEY-HBDS-G-12D1-D

         

        HEY-HBDS-G-12D1-D-fig13

        Figure 13: HEY-HBDS-G-12D1-D Silkscreen and component placement

         

        HEY-HBDS-G-12D1-D-fig14b  HEY-HBDS-G-12D1-D-fig14a  

         

        Figure 14: HEY-HBDS-G-12D1-D-A Top Side Copper (L) and Layer 2 Copper (R)

         

        HEY-HBDS-G-12D1-D-fig15a HEY-HBDS-G-12D1-D-fig15b

         

        Figure 15: HEY-HBDS-G-12D1-CDLayer 2 Copper(L) and Bottom Side Copper (R)

         

         

         

         

         

        Bill of materials

         

        Item

        Ref Name

        Description

        Value

        Qty

        Manufacturer

        Manufacturer PN

        1

        C1, C2

        CAP CERALINK, 1uF,500V PLZT

        1uF

        2

        TDK

        B58031U5105M062

        2

        C14,C15,C16,C17

        CAP, CER,100nF,16V,X7R, S0402

        100nF

        4

        KEMET

        C0402C104K4RALTU

        3

        C3,C4

        CAP, CER, 75pF,50V,NP0, S0402

        75pF

        2

        KEMET

        C0402C750J5GACTU

        4

        C6,C13

        CAP, CER,1uF,25V,X5R, S0402

        1uF

        2

        MURATA

        GRM155R61E105KA12D

        3

        CONN1

        HEADER, 6 WAY, 2.54mm

        6WAY, 2P54

        1

        WURTH

        61300611121

        6

        CR1,CR2

        DIO ZEN, 6V2, 250mW, 2%, SOD882

        BZX884-C6V2

        2

        NEXPERIA

        BZX884-B6V2,315

        7

        IC1,IC2

        GaN FET Driver

        HEY1011-L12C

        2

        HEYDAY IC

        HEY1011-L12

        8

        Q1,Q2

        NGAN GS66516B 650V 60A

        GS66516B

        2

        GAN SYSTEMS

        GS66516B-MR

        9

        R1,R5

        RES, SMD, 10R, 0.063W, 1%, S0402

        10R

        2

        VISHAY

        CRCW040210R0FKED

        10

        R11,R13

        RES, SMD, 3K6, 0.063W, 1%, S0402

        3.6K

        2

        PANASONIC

        ERJ2RKF3601X

        11

        R2

        RES, SMD, 100K, 0.063W, 1%, S0402

        100K

        1

        PANASONIC

        ERJ2GEJ104X

        12

        R3,R7

        RES, SMD, 1R0, 0.063W, 1%, S0402

        1R

        2

        VISHAY

        CRCW04021R00FKED

        13

        R4,R8

        RES, SMD, 0R0, 0.063W, 1%, S0402

        0R

        2

        VISHAY

        RCG04020000Z0ED

        14

        R6,R9

        RES, SMD, 49R9, 0.063W, 1%, S0402

        49R9

        2

        VISHAY

        CRCW040249R9FKED

         

        Table 1: Bill of materials

         

        Ordering information

        Please visit our online store

         

        Disclaimer

        Heyday Integrated Circuits (“Heyday”) provides all data in any resource and in any format such as, but not limited to datasheets, reference designs, application notes, web tools and safety information “as is” and with all faults, and disclaims any type of warranties, fitness for a particular purpose or non-infringement of 3rd party intellectual property rights. Any examples described herein are for illustrative purposes only and are intended to provide customers with the latest, accurate, and in-depth documentation regarding Heyday products and their potential applications. These resources are subject to change without notice. Heyday allows you to use these resources only for development of an application that uses the Heyday product(s) described in the resource. Other reproduction and display of these resources is prohibited. Heyday shall have no liability for the consequences of use of the information supplied herein.

         

         

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