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        DATASHEET

        HD-000071-DS-22-HEY1011- series



        FEATURES

        • Power-ThruTM integrated isolated bias
          • No high-side bootstrap
          • No external secondary-side bias
        • 50-ns propagation delay, with excellent device-to-device matching of 5 ns
        • Separate drive output pins pull-up (2.8 Ω) and pull-down (1.0 Ω)
        • Supply voltage 10.5 V < VDRV < 13.2 V
        • UVLO on primary VDRV and secondary VSEC
        • EN enable pin with fast response
        • Continuous ON capability – no need to recycle IN or recharge bootstrap capacitor
        • CMTI > 100 V/ns dv/dt immunity
        • Creepage distance > 8 mm
        • Distance-through-insulation DTI ≥ 450 μm
        • Safety Regulatory Approvals (pending)
          • 5.7 kV RMS VISO per UL 1577
          • 8 kV pk VIOTM maximum transient isolation voltage per VDE0884-11
          • 630 V pk maximum working isolation voltage

         

        APPLICATIONS 

        • AC-DC and DC-DC converters - Totem-pole PFC, Half-/Full-Bridge, LLC, SR Drive, Multi-level converters, Phase-Shifted Full-Bridge, etc.
        • Automotive – EV chargers, OBC, motor drives
        • Industrial – transportation, robotics
        • Grid Infrastructure – micro-inverters, solar

        GENERAL DESCRIPTION

         

        The HEY1011 isolated gate driver is optimised for driving GaNFETs in multiple applications and topologies. An isolated output bias supply is integrated into the driver device, eliminating the need for any external gate drive auxiliary bias supply or high-side bootstrap. This greatly simplifies the system design and reduces EMI through reduced total common-mode (CM) capacitance. It also allows the driving of a floating switch in any location in a switching power topology.

        The driver has fast propagation delay and high peak source/sink capability to efficiently drive GanFETs in high-frequency designs. High CMTI combined with isolated outputs for both bias power and drive make it ideal in applications requiring isolation, level-shifting, or ground separation for noise immunity.

        The device is available in a compact low-profile surface-mount LGA package. Several protection features are integrated, including UVLO on primary and secondary bias rails, internal pull-down on IN pin and OUTPD pin, fast-response enable input, and OUT pulse synchronisation with first IN rising edge after enable (avoids asynchronous runt pulses).

        Hey1011-xLx trans 150x150

        Figure 1: LGA: 10 x 7.66 x 2.53 mm 12-pin integrated prototype package

         

        Typical application diagram

        Fig2&3_halfbridge_drivers

        Figure 2: Typical HEY1011 Half-Bridge application - eliminates high-side booststrap

        TYPICAL APPLICATIONS

         

        Fig2&3_halfbridge_drivers

        Figure 3: Half-Bridge with HEY1011 as high and low side drivers

         fig4 Totem pole PFC HEY1011

        Figure 4: Totem pole PFC: HEY1011 (GaN version) and HEY2011 (MOS version) as high side  and low side drivers

         

        Fig5_flyback_split_hey1011

        Figure 5: Centre switched Flyback – HEY1011 driving centre tapped switch (symmetrical bipolar voltage swings)

         

         Fig6_flyback_driver_sec_side_control

        Figure 6: Secondary control to primary drive - Hey1011 single driver

         

        Fig7_ev_multilevel_dc-dc_hey1011 

        Figure 7: Multi-Level Converter – stacked low voltage switches results in higher efficiency.  HEY1011 makes this easy to drive.

         

        INTERNAL BLOCK DIAGRAM

        fig8 driver_blockdiagram_01 v20

        Figure 8: HEY1011 Block Diagram

         

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        PIN DESCRIPTIONS

         

        Pin

        Number

        Pin

        Name

        Pin Function

        1

        GND

        Internally connected to GND; recommend external connection to GND net (pin 6) to improve thermal impedance; can be left floating if necessary.

        2

        SEL

        Internal use only - this pin MUST be tied high to VDRV

        3

        EN

        Bidirectional enable pin, figure 9

        4

        IN

        PWM input. Table 7

        5

        VDRV

        Ground referenced voltage supply.  This bias voltage directly sets the output gate drive amplitude.

        6

        GND

        Ground pin for input/primary side

        7

        OUTSS

        Internally connected to OUTSS; recommend external connection to OUTSS net (pins 9, 10) to improve thermal impedance; can be left floating if necessary. See section bipolar output drive

        8

        VSEC

        External capacitor referenced to OUTSS. 

        9

        OUTSS

        Isolated output return pin

        10

        OUTSS

        Isolated output return pin

        11

        OUTPD

        Isolated output drive pull-down pin. Table 7

        12

        OUTPU

        Isolated output drive pull-up pin. Table 7

        Table 1: HEY1011 Pin Descriptions

         

        SPECIFICATIONS

        Absolute Maximum Ratings(1)

         

        Symbol

        Parameter

        Min

        Max

        Unit

        VDRV

        Drive supply voltage VDRV to GND

        GND - 0.5V

        15

        V

        IN

        Input data, IN to GND

        GND - 0.5V

        15

        V

        EN

        Enable, EN to GND

        GND - 0.5V

        15

        V

        SEL

        Internal use only, SEL to GND

        GND - 0.5V

        15

        V

        OUTPU

        Output drive pull up, OUTPU to OUTSS

        OUTSS - 0.5V

        15

        V

        OUTPD

        Output drive pull down, OUTPU to OUTSS

        OUTSS - 0.5V

        15

        V

        VSEC

        Isolated bias supply, VSEC to OUTSS

        OUTSS - 0.5V

        15

        V

        Tj

        Junction Temperature

        -40

        150

        °C

        (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

        Table 2: Absolute Maximum Ratings

         

        ESD Ratings

        Electrostatic Discharge Value Unit
        VESD Human body model (HBM) ±2 kV
        Charge Device Model (CDM) ±500 V

        Table 3: ESD Ratings

         

        Thermal Information

         

        Symbol

        Parameter

        Value

        Unit

        RqJA

        Junction-to-ambient thermal resistance

        tbd

        °C/W

        RqJC

        Junction-to-case thermal resistance

        tbd

        °C/W

        Table 4: Thermal Information

         

        Recommended Operating Conditions

        -40°C <TJ< 125°C, 10.5V < VDRV < 13.2V. Csec = 22nF, Cout. = 1nF, Unless otherwise stated.

         

        Symbol

        Parameter

        Condition

        Min

        Typ

        Max

        Unit

        Supply voltage Pins

        VDRV

        Drive supply voltage

        see table 10

        10.5

         

        13.2

        V

        Input Pins

        IN

        Input Data

         

        GND

         

        VDRV

        V

        EN

        Enable Active High

         

        GND

         

        VDRV

        V

        SEL

        Internal use only

         

        GND

         

        VDRV

        V

        Output Pins

        OUTPU

        Output pull-up

         

        0

         

        13.2

        V

        OUTPD

        Output pull-down

         

        0

         

        13.2

        V

        VSEC

        Isolated supply referenced to OUTSS

         

        0

         

        13.2

        V

        TJ

        Junction Temperature

         

        -40

         

        125

        °C

        Table 5: Recommended Operating Conditions

         

         

        VSEC Pin Capacitor

        -40°C <TJ< 125°C, 10.5V < VDRV < 13.2V, Csec = 22nF, Cout. = 1nF, Unless otherwise stated.

        Symbol

        Parameter

        Condition

        Min

        Typ

        Max

        Unit

        VSEC pin capacitor CSEC

        CSEC

        External capacitance connected between CSEC and OUTSS pins

        External switch

        CISS = 1nF

        5

        Note1

        27

         

        100

        Note 2

        nF

        Table 6: Choosing CSEC capacitor value

        1. Smaller CSEC values than the recommended typical value can give higher voltage ripple on CSEC
        2. Larger CSEC values will mean longer start up times.

         

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        Electrical Characteristics

        -40°C <TJ< 125°C, 10.5V < VDRV < 13.2V, Csec = 22nF, Cout. = 1nF, Unless otherwise stated.

         

        Symbol

        Parameter

        Condition

        Min

        Typ

        Max

        Unit

        Supply Currents

        IDRV_Q

        VDRV quiescent current

        IN=0, VDRV = 12V

         

        2

         

        mA

        IDRV_SW

        VDRV switching current

        FS = 100 kHz,  VDRV= 12V

         

        4.2

         

        mA

        Input Pins

        IN

        Input Data

        Logic low

        Logic High

         

        2.0

         

        1.0

         

        V

        Hysteresis

         

         

        300

         

        mV

        EN

        Enable Active High

        Logic low

        Logic High

         

        2.0

         

        1.0

         

        V

        V

        Hysteresis

         

         

        400

         

        mV

        RIN

        Internal on-chip pull-down resistance on IN pin

        Always present

         

        300

         

        Output Pins

        RPU

        OUTPU pull up resistance

         

         

        2.8

         

        Ω

        RPD

        OUTPD pull down resistance

         

         

        1.0

         

        Ω

        ISOURCE

        High level source current

        VSEC=10V, Rext_PU=0Ω, COUT=10nF, see note 1

         

        2

         

        A

        ISINK

        Low level sink current

        VSEC=10V, Rext_pd=0Ω, COUT=10nF, see note 1

         

        4

         

        A

        Primary Under Voltage Lock Out

        VDRV_UV

        VDRV UV Threshold, rising

        Note 2

        9.5

        10.0

        10.5

        V

        VDRV_UVH

        VDRV UV Hysteresis

         

         

        0.7

         

        V

        Secondary Under Voltage Lock Out

        VSEC_UV

        VSEC UV Threshold, rising

         

        3.9

        4.3

        4.8

        V

        VSEC_UVH

        VSEC UV Hysteresis

         

         

        0.3

         

        V

        1. Not tested in production; guaranteed by design and bench characterisation. 
        2. When VDRV is below the UVLO threshold the driver output is actively held low.

          Table 7: HEY1011 Electrical Characteristics

        Switching Characteristics

        -40°C <TJ< 125°C, 10.5V < VDRV < 13.2V, Csec = 22nF, Cout. = 1nF, Unless otherwise stated.

         

        Symbol

        Parameter

        Condition

        Min

        Typ

        Max

        Unit

        Propagation Times

        TPHL

        Propagation delay, high to low

         

         

        50

         

        ns

        TPLH

        Propagation delay, low to high

         

         

        50

         

        ns

        TPM

        Propagation matching

        Part to part

         

        5

         

        ns

        Rise and Fall times

        tr

        Rise time

        REXT_PU = 0 Ω, 20-80%

         

        9

         

        ns

        tf

        Fall time

        REXT_PD = 0 Ω, 20-80%

         

        7

         

        ns

        tpw,on

        Shortest ON time allowable

         

        50

         

         

        ns

        tpw,off

        Shortest OFF time allowable

         

        150

         

         

        ns

        Start up time

        TSTART

        Wait time before first IN edge is delivered after VDRV is within specification

         

         

         

        500

        µs

        Table 8: HEY1011 Switching Characteristics

         

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        APPLICATION INFORMATION

        Primary UVLO voltage selection

         

        SEL Connection

        Typical UVLO (V)

        GND

        6.5

        VDRV

        10

        Table 9: HEY1011 UVLO Selection

        The SEL pin selects the under-voltage lock-out level for the VDRV supply. This is done by connecting the SEL pin to GND or VDRV to select the desired nominal UVLO level per Table 9. Detailed UVLO specs are given in Table 7.

        .

        APPLICATIONS INFORMATION

        Bidirectional Enable/Disable

        EN is a bidirectional open-drain pin which requires an external resistor pull-up to the VDRV pin. The EN pin allows for management of start-up and fault conditions between the PWM controller and multiple HEY1011 drivers, through use of a shared enable EN line. Either the PWM controller or the driver can pull the EN pin low via the EN bus, as shown in Figure 9. When the EN pin is pulled low (either externally or internally), this forces the driver into a mode where the IN pin signal is ignored, and the OUT pins are disabled and actively pulled low. When the EN pin goes high, normal driver operation is enabled.

        In the event of an internal driver fault condition, such as UVLO or normal start-up delay, the EN pin is actively pulled low internally by the driver. This driver pull-down can be detected by the PWM controller and used as a flag for an external fault, or to flag that the driver is ready, and PWM can commence.

        The shared EN line is typically wired-AND with the controller Enable pin, as shown in Figure 9. Multiple HEY1011 drivers can be connected in parallel with the controller on the shared EN line, such that which means that all connected drivers will hold the EN line low until all drivers and the PWM controller have released their own EN pin, ensuring smooth safe start-up of the system.

         Fig9_patent_prim_enable_hey1011

        Figure 9: Example ‘Wired AND’ connection between driver and controller

        The shared EN line is typically wired-AND with the controller Enable pin, as shown in Figure 9. Multiple HEY1011 drivers can be connected in parallel with the controller on the shared EN line, such that which means that all connected drivers will hold the EN line low until all drivers and the PWM controller have released their own EN pin, ensuring smooth safe start-up of the system.

        Note that the EN pin has no internal pull-up or pull-down – the open-drain configuration relies on an external pull-up resistor for normal operation. Similarly, the EN pin must be actively pulled low externally to disable the driver. The EN pin should never be left floating. If not used, the EN pin should be connected to VDRV through a pull-up resistor in a recommended range of 10-100 kΩ. The EN pin dv/dt when being pulled low or high should be at least 0.1 V/μs.


        When the EN pin is pulled low, the driver output is disabled, and pulls down the OUTPD pin, regardless of the IN pin level (high or low). The driver goes to a low-power standby mode, and the isolated VSEC bias rail is allowed to discharge. The rate of decay of VSEC depends on the value of the CSEC capacitor.


        When the EN pin is subsequently pulled high, the driver will re-enable, and the isolated VSEC bias rail will start to recharge. Even if the IN pin is connected to a PWM signal, the OUT pins will not respond until the VSEC rail exceeds the secondary UVLO threshold. The rate of rise of VSEC depends on the PWM frequency at the IN pin. Worst case slowest rise time is when IN = 0, using the slowest internal energy-transfer mode. In this mode the rise time will be approximately 80 μs for CSEC of 47 nF to charge from zero to the rising UVLO threshold.

         

        Start up procedure

        Fig10_Start-up hey1011

        Figure 10: HEY1011 Start-up relationship to be observed between VDRV, EN and IN PWM signal

        Any PWM signal applied to IN must remain low until VDRV > UV threshold, to avoid parasitic charging of the VDRV rail through the IN pin internal ESD structures. After VDRV exceeds the UV enable threshold, a start-up time delay Tstart is required, to charge VSEC and allow all internal circuits to initialise and stabilise. During Tstart, any IN signal inputs are ignored. EN internal pull-down will remain active during Tstart, and will disable (i.e. go open-drain) only when VDRV has reached its UVLO voltage level, all on-chip voltages are stabilised and the internal Tstart timer has elapsed. This the EN pin can be used via a shared EN line to flag when Tstart has elapsed, and the driver is ready to respond to PWM signals at the IN pin, as outlined above.

         

        Operating Frequency

        The maximum allowable operating frequency of the HEY1011 is dependent on the operating ambient air temperature, VDRV voltage level, and the gate charge of the external GaN FET being driven at the OUTPU/OUTPD pins. The total power transferred from VDRV voltage on the primary to the external GaN FET on the secondary increases with gate drive switching frequency and VDRV voltage, hence the IC package must dissipate more heat. The safe operating frequency range is shown in Figure 11, along with the stated values for CLOAD (effective capacitive loading due to the external GaN FET gate), CSEC and VDRV voltage.

        Fig11_Safe operating area hey1011

        Figure 11:HEY1011 Safe operating PWM frequency versus ambient air temperature

         

        VDRV and CSEC Design Guidelines

         

         The output gate drive amplitude is always less than the VDRV voltage.

        The OUTPU gate voltage level depends on factors such as VDRV level, CLOAD and CSEC. Figure 12 shows the typical output gate drive amplitude as a function of VDRV and CLOAD, for an assumed value of CSEC as a multiple of CLOAD, for a 50% duty cycle PWM at the IN pin.

        Fig12_Vsec-vs-Vdrv

        Figure 12: Typical Vgate voltage versus VDRV voltage for 4 CLOAD capacitors

        Conditions for Figure 12: FIN =100kHz, D = 50%, CSEC = 20*CLOAD

         

        The recommended value for CSEC is approximately 10-20 times CLOAD (the equivalent gate capacitance), to give approximately 5-10% switching ripple on the VSEC rail. Other values can be used, however lower values will result is higher ripple on VSEC. Larger CSEC will require a longer startup time. The maximum recommended value of CSEC = 100 nF should not be exceeded

         

        Bipolar Output Drive

        Bipolar output drive is used to provide a negative gate voltage which can be beneficial in protecting against false turn on due to parasitic circuits components. It can be added simply to the HEY1011 by including three extra small external components. For full details see the Heyday application note HD-000222-AN.

        Fig13a_Hey1011 Bipolar Gate SCH.          Fig13b_Hey1011 Bipolar Gate PCB Layout

         

        Figure 13: HEY1011 Bipolar drive and recommended PCB layout

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        PACKAGE OUTLINE

        Fig14_HD-000342-MD-A HEY1011-L12 - Datasheet Drawing ONLY v2 Sheet1

        Figure 14: HEY1011 Package Outline

         

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        RECOMMENDED PCB FOOTPRINT

        Fig15_LGA 10X7p66 PCB Footprint

        Figure 15: Recommended PCB footprint

         

        REGULATORY INFORMATION (pending)

         

        Safety Certification Standards

        • UL1577 Component safety (optical and digital isolators)
        • VDE0884-11 Component safety (digital isolators)

        Specification

        Parameter

        Target

        Specification

        Specification detail and comments

        VISO

        5700 VRMS

        Withstand isolation voltage per UL 1577

        VIOTM

        8000 VPK

        Maximum transient isolation voltage per VDEE0884-10

        VIORM

        630 VPK

        Maximum working isolation voltage

        CIO

        < 1 pF

        Barrier capacitance, two terminal device connection

        RIO

        > 1012Ω

        Isolation resistance, two terminal device

        DTI

        > 100 µm

        Distance through isolation

        Creepage

        > 8 mm

        External package creepage

        Clearance

        > 8 mm

        External package clearance

        Table 9: Target Regulatory Specifications

        ORDERING INFORMATION

         

        Driver

        Switch

        #channels

        Output

        Isolation

        package

        HEY1011-L12N0

        GaN driver

        1

        Unipolar

        Functional

        LGA 12 pin

        HEY1011-L12V0

        GaN driver

        1

        Unipolar

        Isolated

        LGA 12 pin

        Table 10: Device ordering information

        MSL RATING

         

        Device

        MSL Rating

        Maximum floor life at ambient (30°C/60%RH)

        Maximum peak reflow temperature

        Pre-reflow bake requirement

        HEY1011-L12 

        MSL-3

        168 hours

        260°C

        Per JEDEC J-STD-033C

        Table 11: MSL and maximum peak reflow temperature

        Per JEDEC J-STD-033C, the HEY1011-L12 devices are rated MSL3. This applies to both advance Alpha samples (HEY1011-L12C) and final production release devices.

        This MSL3 rating means that once the sealed production packaging is opened, the devices must be reflowed within a “floor-life” of 168 hours (1 week) if they are stored in under standard ambient conditions (30°C and 60% relative humidity (RH)).

        The peak reflow temperature should not exceed the maximum specified in Table 11.

        If the devices are exposed to the standard ambient for more than 168 hours, they must be baked before reflow, to remove any excess moisture in the package and prevent damage during reflow soldering. The required bake times and temperatures are detailed in IPC/JEDEC standard J-STD-033C.

        If the devices are exposed to higher temperature and/or RH compared to the standard ambient of 30°C/60% RH, the floor-life will be shortened due to the increased rate of moisture absorption. If the actual ambient conditions exceed the standard ambient, it is recommended that parts should always be baked per IEC/JEDEC J-STD-033C before reflow, as a precaution to avoid potential device damage during reflow soldering.

        Disclaimer

        Heyday Integrated Circuits (“Heyday”) provides all data in any resource and in any format such as, but not limited to datasheets, reference designs, application notes, web tools and safety information “as is” and with all faults, and disclaims any type of warranties, fitness for a particular purpose or non-infringement of 3rd party intellectual property rights. Any examples described herein are for illustrative purposes only and are intended to provide customers with the latest, accurate, and in-depth documentation regarding Heyday products and their potential applications. These resources are subject to change without notice. Heyday allows you to use these resources only for development of an application that uses the Heyday product(s) described in the resource. Other reproduction and display of these resources is prohibited. Heyday shall have no liability for the consequences of use of the information supplied herein.

         

         

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