Datasheet

HD-000157-DS-4-HEY1011-L12A

Hey1011-NL12A ISO 600x400 trans
24 min read

Hey1011-L12A-Engineering Samples - floating isolated ganfet driver

Nov 25, 2019 12:00:00 AM

CONTENT 

Features - Applications - Description - Block diagram - Typical applications - Pin Descriptions - Specifications - Absolute Maximum Ratings - ESD Ratings - Recommended Operating Conditions - Thermal Information - Electrical Characteristics - CSEC Capacitor - Switching Characteristics - UVLO Voltage selection - Enable/Disable bidirectional - Test Circuits - Vdrv and Csec design guidelines - Package Outline - Recommended PCB Footprint - Regulatory information (pending) - Ordering Information - Download

This is an Engineering sample datasheet. The HEY1011-L12A has the following specifications reduced for these samples only.

  1. Vdrv has been reduced from 15V to 10V maximum.

  2. fmax has been reduced to 1MHz maximum

 FEATURES

  • Floating 650V isolated driver for high-voltage GaN FET’s
  • No bootstrap components or isolated supply required.
  • >100V/ns dv/dt immunity (CMTI)
  • 50ns propagation delay with excellent device-to-device matching of 5ns
  • Separate pull-up/ down drive output pins. Pull-down impedance: 1.0Ω. Pull-up impedance:  2.8Ω
  • ≥ 100μm Distance through isolation (DTI)
  • 7.5V < VDRIVE < 15V.
  • First pulse perfect – first drive pulse within specification
  • Continuous ON time capability – no need to recycle drive
  • Output drive pins OUTPU, OUTPD and OUTSS can swing ± 5kV with respect to GND
  • Safety-Related and Regulatory Approvals (planned)
    • 5700VRMS Withstand isolation voltage per UL 1577
    • 8000VPK Maximum transient isolation voltage per VDE0884-10
    • 630VPK Maximum working isolation voltage

APPLICATIONS 

  • Totem Pole PFC, Half/ Full-Bridge, LLC, SR Drivers, Multi-level converters using stacked switches
  • Secondary side control to primary drives
  • Automotive

DESCRIPTION

fig01 LGA package

Figure 1: LGA: 10 x 7.66 x 2.64mm 12-pin integrated prototype package

 

 

BLOCK DIAGRAM

fig2 block diagram

Figure 2: HEY1011 Block Diagram

 

 

TYPICAL APPLICATIONS

fig3 half-bridge

Figure 3: Half-Bridge with Hey1011 as high and low side drivers

 

 fig4 totem pole

Figure 4: Totem pole PFC: Hey1011 and Hey1012 as high and low side drivers

 

 

 fig5 secondary control to primary drive

Figure 5: Secondary control to primary drive - Hey1011 single driver

 

 

fig6 centre switched flyback

Figure 6: Centre switched Flyback – Hey1011 driving centre tapped switch (symmetrical bipolar voltage swings)

 

 

 

fig7 multi-level converter 

Figure 7: Multi-Level Converter – stacked low voltage switches results in higher efficiency.  Hey1011 makes this drive easy.

 

PIN DESCRIPTIONS

 

Pin

Number

Pin

Name

Pin Function

1

N/C

Reserved

2

UVLO SEL

Sets the UVLO voltage. External resistor referenced to GND.

3

EN

Bidirectional enable pin 

4

IN

PWM input

5

VDRV

Ground referenced bias voltage supply.  This bias voltage directly sets the output gate drive amplitude.

6

GND

Ground pin

7

RESERVED

Must be connected to OUTSS

8

CSEC

External capacitor referenced to OUTSS. 

9

OUTSS

Floating output reference pin

10

OUTSS

Floating output reference pin

11

OUTPD

Floating output pull-down pin

12

OUTPU

Floating output pull-up pin

Table 1: HEY1011 Pin Descriptions

 

 

SPECIFICATIONS

Absolute Maximum Ratings

 

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Operating Conditions

VDRV

Drive supply voltage

 

GND - 0.5V

 

17

V

IN

Input data

 

GND - 0.5V

 

17

V

EN

Enable

 

GND - 0.5V

 

17

V

MODE

Mode setting

 

GND - 0.5V

 

3.6

V

OUTPU

Output pull up

 

OUTSS - 0.5V

 

17

V

OUTPD

Output pull down

 

OUTSS - 0.5V

 

17

V

CSEC

Floating supply

 

OUTSS - 0.5V

 

17

V

Tj

Junction Temperature

 

-40

 

150

°C

Table 2: Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

 

ESD Ratings

 

 

Value

Unit

ESD

Human body model (HBM)

2

kV

Charge Device Model (CDM)

500

V

Table 3: ESD Ratings

Recommended Operating Conditions

-40°C <TJ< 125°C, 7.5V < VDRV < 15V. Unless otherwise stated.

 

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Operating Conditions

VDRV

Drive supply voltage

 

7.5

 

15

V

Input Pins

IN

Input Data

 

GND

 

VDRV

V

EN

Enable Active High

 

GND

 

VDRV

V

MODE

Mode setting pin

 

GND

 

3.3

V

Output Pins

OUTPU

Output pull-up

 

0

 

15

V

OUTPD

Output pull-down

 

0

 

15

V

CSEC

Floating supply referenced to OUTSS

 

0

 

15

V

TJ

Junction Temperature

 

-40

 

125

°C

Table 4: Recommended Operating Conditions

 

Thermal Information

 

Symbol

Parameter

Value

Unit

RqJA

Junction-to-ambient thermal resistance

tbd

°C/W

RqJC

Junction-to-case thermal resistance

tbd

°C/W

Table 5: Thermal Information

 

 

Electrical Characteristics

-40°C <TJ< 125°C, 5.5V < VDRV < 15V. Unless otherwise stated.

 

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Supply Currents

IS DRV

VDRV static current

IN=0, MODE=0, VDRV=7.5V

 

1000

 

µA

ID DRV

VDRV switching current

FS = 100 kHz

CLOAD = 1nF (see plot), VDRV=7V

 

3

 

mA

Input Pins

IN

Input Data

Logic low

Logic High

 

2.0

 

1.0

 

V

Hysteresis

 

300

 

 

mV

EN

Enable Active High

Logic low

Logic High

 

2.0

 

1.0

 

V

V

Hysteresis

 

400

 

 

mV

MODE

Mode Setting Pin

 

GND

 

3.6

V

RIN

IN pin input pull down resistance on chip

Always present

 

300

 

Output Pins

RPU

OUTPU pull up resistance

 

 

2.8

 

W

RPD

OUTPD pull down resistance

 

 

1.0

 

W

ISOURCE

High level source current

VSEC=10V, RPU=0Ω, CLOAD=10nF, Note 3

 

2

 

A

ISINK

Low level sink current

VSEC=10V, RPU=0Ω, CLOAD=10nF, Note 3

 

4

 

A

Under Voltage Lock Out

VUV

VDRV Threshold

(voltage falling)

Note 1

Note 2

3.9

9.5

4.15

10.0

4.4

10.5

V

VUVH

VDRV Threshold Hysteresis

For 4.15V threshold

For 10V threshold

 

0.3

0.7

 

V

Table 6: HEY1011 Electrical Characteristics

  1. When Vdrv falls below the UVLO threshold the driver output is driven and held low.
  2. The UVLO trip point is programmable using the MODE pin. See Table 9: HEY1011 Operating Modes.
  3. See test circuit in Test Circuit section of datasheet.

 

CSEC Capacitor

-40°C <TJ< 125°C, 7.5V < VDRV < 15V. Unless otherwise stated.

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Capacitor CSEC

CSEC

External capacitance connected between CSEC and OUTSS pins

External switch

CISS = 1nF

5

Note1

27

 

100

Note 2

nF

               

Table 7: Choosing CSEC capacitor value

  1. Smaller CSEC values than the recommended typical value can be used but hold-up time on OUTPU and OUTPD will be reduced.
  2. Larger CSEC values will mean longer start up times.

 

 

Switching Characteristics

-40°C <TJ< 125°C, 5.5V < VDRV < 15V. Unless otherwise stated.

 

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Propagation Times

TPHL

Propagation delay, high to low

(IN to TXPP,TXPN)

Resistive load of 1k between TXPP and TXPN

 

50

 

ns

TPLH

Propagation delay, low to high

(IN to TXPP,TXPN)

Resistive load of 1k between TXPP and TXPN

 

50

 

ns

TPM

Propagation matching

(IN to TXPP,TXPN)

Part to part

 

5

 

ns

Rise and Fall times

tr

Rise time

CLOAD = 1nF

REXT = 100mW

20-80%

 

9

 

ns

tf

Fall time

CLOAD = 1nF

REXT = 100mW

20-80%

 

7

 

ns

tpw

Minimum input pulse width that makes output change

 

 

50

 

ns

Start up time

TSTART

Wait time before first IN edge is delivered after VDRV is within specification

 

 

 

450

µs

Table 8: HEY1011 Switching Characteristics

 

UVLO VOLTAGE sELECTION

 

RUVLO

UVLO (V)

Short Circuit

4.15

2.7kΩ

10

Table 9: HEY1011 UVLO Selection

 

 

ENABLE/DISABLE bIDIRECITONAL

When the enable pin is externally driven low this forces the driver into a low power mode.  The output is pulled low in this mode.  When the enable pin is driven high this forces the driver into normal operating mode.  In the event of an internal fault condition, such as UVLO, this pin is actively pulled low by the driver.  This information can be used by the controller, for example, as required.  It is typically wired AND with the controller Enable pin as shown in Figure 8 below.

 fig8 example wired AND connection

Figure 8: Example ‘Wired AND’ connection between driver and controller

 

TEST CIRCUITS

 

Test circuit for measuring Isink and Isrc is shown below.  (To be added).

 

VDRV aND CSEC DESIGN GUIDELINES

 

 

The output gate drive amplitude is always less than the Vdrv voltage. 

The OUTPU gate voltage depend on factors such as VDRV, CLOAD and CSEC. Figure 9 shows the typical output gate drive amplitude as a function of VDRV and Cload. 

Hey1011 DS graph9

Figure 9: Typical Vgate voltage versus Vdrv voltage for 4 Cload capacitors

Conditions for Figure 9 : FIN =100kHz, D = 50%, UVLO = 4.15V, CSEC = 20*CLOAD

 

Hey1011 DS graph10

Figure 10: Minimum Vgate voltage versus Vdrv voltage for 4 Cload capacitors

Conditions for Figure 10: FIN =120kHz, TIN-ON = 50ns, UVLO = 4.15V, CSEC = 20*CLOAD

 

The following operating conditions are suggested to guarantee optimal operation:

CLoad

CSEC

Minimum Vdrv

1n

22n

7.5V

2.2n

22n

8.5V

47n

8.5V

4.7n

47n

10.5V

100n

10.5V

10n

100n

15V

Table 10: suggested CSEC and VDRV values

 

Those suggestions take into account the typical and worst use cases. The suggested Csec and VDRV provide a minimum of 5V on the OUTPU pin regardless of the input pattern.

The Csec value associated with each Cload is given as a suggestion. Many values are possible, but it is recommended that Csec is at least 10*Cload.  Larger Csec implies a longer starting time. The Csec = 100nF value should not be exceeded.

 

 

 

PACKAGE OUTLINE

fig9 package outline

Figure 11: HEY1011 Package Outline

 

RECOMMENDED PCB FOOTPRINT

fig10 recommneded footprint

Figure 12: Recommended PCB footprint

 

 

 

REGULATORY INFORMATION (pending)

Safety Certification Standards

IMPORTANT: The breakdown isolation voltages for these engineering samples is not guaranteed.

  • UL1577 Component safety (optical and digital isolators)
  • VDE0884-10 Component safety (digital isolators)

 

Specification

Parameter

Target

Specification

Specification detail and comments

VISO

5700 VRMS

Withstand isolation voltage per UL 1577

VIOTM

8000 VPK

Maximum transient isolation voltage per VDEE0884-10

VIORM

630 VPK

Maximum working isolation voltage

CIO

1pF

Barrier capacitance, two terminal device connection

RIO

>1012Ω

Isolation resistance, two terminal device

DTI

>100µm

Distance through isolation (expandable)

Creepage

>8mm

External package creepage

Clearance

>8mm

External package clearance

Specification

Parameter

Target

Specification

Specification detail and comments

Table 11: Target Regulatory Specifications

 

ORDERING INFORMATION

 

Driver

Switch

#channels

Output

Isolation

package

HEY1011-NL12

GaN driver

1

Unipolar

Floating

LGA 12 pin

HEY1011-AL12

GaN driver

1

Unipolar

Isolated

LGA 12 pin

 

DISCLAIMER

Heyday Integrated Circuits (“Heyday”) provides all data in any resource and in any format such as, but not limited to datasheets, reference designs, application notes, web tools and safety information “as is” and with all faults, and disclaims any type of warranties, fitness for a particular purpose or non-infringement of 3rd party intellectual property rights. Any examples described herein are for illustrative purposes only and are intended to provide customers with the latest, accurate, and in-depth documentation regarding Heyday products and their potential applications. These resources are subject to change without notice. Heyday allows you to use these resources only for development of an application that uses the Heyday product(s) described in the resource. Other reproduction and display of these resources is prohibited. Heyday shall have no liability for the consequences of use of the information supplied herein.

 

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