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        Application note

        By GaN Systems, published in BODO Power Magazine, Dec 2021

         

        Seven Steps To Highly Effective GaN Designs

        Today, we operate in a very fast-moving world, looking for shortcuts, opportunities to “copy and paste” to complete tasks in a short period of time. Although GaN power transistors are relatively new, design “rules of thumb” has been established and proven to meet fast time-to-market objectives. Over the years, seven steps to a successful design have been developed and proven – backed by ongoing and updated documentation and customer training.

        By Juncheng (Lucas) Lu, GaN Systems Applications Engineering Manager, GaN Systems

        This article provides an overview of these seven steps and links to application notes to inform users and customers of the latest information needed to optimize their GaN designs.

        Step 1 – Gate Drive Selection

        Driving the gates of GaN enhancement mode high electron mobility transistors (E-HEMTs) has similarities in common with driving the gates of silicon (Si) MOSFETs – but with a few beneficial differences.

        Driving GaN E-HEMTs does not eliminate any popular Si gate drivers; they simply make GaN easier and more effective to use. This means high-voltage (>600V) quasi-resonant and fixed frequency flyback adapters, chargers, and other low-power AC/DC controllers can be used for different LLC and power factor correction (PFC) configurations in GaN designs.

        Simple circuitry provides the transition capability for using a Si controller for GaN devices. For a single GaN device, the isolated, negative VGS(OFF) EZDrive® circuit is a low-cost, easy way to use a 12V driver to drive a 6V GaN transistor for use with any controller or driver with single, dual, or high-side/low-side drivers.

        A new driver, the Heyday HEY1011, provides significant size reduction and board space savings in GaN designs. With its ability to eliminate bootstrap and isolated supplies, it is also the smallest isolated gate drive solution in the market. Figure 1 shows an evaluation board using a HEY1011 with an integrated power rail.

        bp_2021_12_p32-GaNSystems-article fig1

        Figure 1: The GS EVB HB 66516B HD, a 650 V GaN E-Mode half-bridge evaluation board,

        features a HEY1011 L12C gate drive solution.

         

        Step 2 – Topology and Schematic Review

        Designers need to constantly be on the lookout for the newest products since using an available, compatible controller simplifies the GaN designer’s task. Depending on the desired topology, such as critical conduction mode (CrM) or continuous conduction mode (CCM), an appropriate controller may already exist and be part of an evaluation tool. For example, an onsemi NCP1680 CrM analog bridgeless totem pole (BTP) PFC controller used in a 300W GaN evaluation demo board shown in Figure 2 results in high efficiency.

        As illustrated, 99% efficiency was achieved at full load at the highest (265V) voltage (plus, the controller’s design includes features for more efficient operation under light loads.)

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