You will find here answers to frequently asked questions. Don't find an answer? Please contact us
It's mixed signal : analog & digital with efficient magnetic isolation
It's standard Silicon Psub wafer.
It is not SOI
The transfer ratio is less than 1:1 and is non linear, depending mainly on the choice of CSEC. An upcoming version of the data sheet will publish the relationship between CSEC and the output gate drive. Internally the secondary side UVLO is 4.8V max although there are plans to reduce this.
The HEY1011-L12A is suitable for an external negative drive circuit as GaN systems have published. It is on our roadmap to have a fully incorporated bipolar device which will be available in 2021.
The dynamic supply current is a function of load capacitance, supply voltage, operating frequency and operating mode. Full characterisation testing is ongoing on these devices and is nearing completion. The datasheet will be revised with full static and dynamic curves being published.
ID DRV of 3mA was an initial design specification and can be achieved under certain operating conditions however a figure of 5 to 6mA will be more typical at 7V/100kHz/1nF. This is the full current into the VDRV pin during operation.
Full characterisation testing is ongoing on these devices and is nearing completion. The datasheet will be revised with full static and dynamic curves being published.
This will include thermal performance information.